ApogeoRV Datasheet

• Introduction
  • Overview
  • Features
  • Target Application
  • Parameters
• External Interface
  • Memory Interface
    • Fetch Channel
    • Load Channel
    • Store Channel
  • Interrupt Interface
  • Trace Interface
• General Architecture
  • Instruction Set Architecture
  • Pipeline General Description
  • Memory Map
    • Boot Region
    • IO Region
    • Privileged General Purpose Memory Region
    • Private Region Overview
    • User Memory Region
  • Input Output
• Control Status Registers
  • CSR List
  • Machine Mode CSRs
    • ISA CSR
    • ID CSRs
    • Status CSR
    • Trap-Vector CSR
    • Interrupt Status CSRs
    • Exception Program Counter CSR
    • Exception Cause CSR
    • Hardware Performance Monitor CSRs
    • Counter-Enable CSR
    • Counter-Inhibit CSR
    • Scratch Register
    • Time Register
  • User Mode CSRs
    • Floating Point Register
• Interrupts And Exceptions
  • Exceptions
  • Interrupts
• Frontend
  • PC Generation Stage
    • Next PC Logic
    • Branch Predictor
    • Instruction Buffer
    • Instruction Misaligned Manager
    • Decompressor
  • Decode Stage
    • Decoder
  • Issue Stage
    • Scheduler
• Backend
  • Bypass Stage
  • Execution Stage
    • Integer Unit
      • Arithmetic Logic Unit
      • Multiplication Unit
      • Division Unit
      • Bit Manipulation Unit
    • Control Status Registers Unit
    • Load Store Unit
      • Load Unit
      • Store Unit
    • Floating Point Unit
      • Floating Point Addition Unit
      • Floating Point Multiplication Unit
      • Comparison Unit
      • Conversion Unit
      • Miscellaneous Unit
      • Rounding Unit
  • Commit Stage
  • Reorder Stage
  • Writeback Stage
• License